1. Field of the Invention
The present invention relates to a network processor, and particularly to a network processor for performing a DMA (Direct Memory Access) transfer.
2. Description of Related Art
The DMA transfer is a technique for transferring data directly to a memory without being accompanied by any arithmetic operation of a CPU (Central Processing
Unit). Load on the CPU is required to be reduced in order to cope with higher-speed operation of a computer system. In addition, a memory access time is also required to be reduced. The DMA transfer plays an increasingly important role as a technique for solving these problems. Techniques related to such a DMA transfer have been disclosed as follows.
Patent Document 1 (Japanese Patent Application Laid Open No. Hei 6-096007) has disclosed a DMA transfer method which, after a DMA transfer based on current transfer control information is completed, is capable of reducing a time needed to load subsequent transfer control information.
FIG. 1 is a drawing showing a block diagram for implementing a DMA transfer method according to Patent Document 1 (Japanese Patent Application Laid Open No. Hei 6-096007).
As shown in FIG. 1, a CPU 11, an input/output unit 12, a RAM 28 as means for storing transmitted data, a RAM 29 as means for storing transfer control information, and a DMA controlling unit 24 as DMA control means are connected together through a data bus 1, an address bus 2 and a control bus 3. The DMA control unit 24 includes: a control register 26 as control storage means; a fetch circuit 27 as pre-fetch means; and a DMA control circuit 25. Multiple successive sets of 4-byte transfer control information (descriptors) which start at a predetermined address are stored in the RAM 29. From FIG. 1, it is learned that sets of 4-byte information which start at an address (0000) are successively stored in the RAM 29. In FIG. 1, reference sign “H” denotes a hexadecimal numeration system.
As described above, multiple sets of transfer control information are beforehand stored in the respective successive addresses in the RAM 29. The DMA control unit 24 loads sets of transfer control information one by one into the control register 26. Once a request for a DMA transfer occurs in the CPU 11 or the input/output unit 12, the DMA control unit 24 performs the DMA transfer on the basis of the set of transfer control information loaded into the control register 26. In addition, the DMA control unit 24 beforehand loads a set of transfer control information subsequent to the current set of transfer control information that is stored in the control register 26, from the RAM 29 to the fetch circuit 27 included in the DMA control unit 24. Once the DMA control unit 24 completes the DMA transfer on the basis of the current set of transfer control information, the DMA control unit 24 loads the subsequent set of transfer control information from the fetch circuit 27 to the control register 26.
In the DMA transfer method according to Patent Document 1, the DMA control unit 24 beforehand loads to the fetch circuit 27 the set of transfer control information subsequent to the current set of transfer control information that is stored in the control register 26. Thereafter, upon completion of the DMA transfer based on the current set of transfer control information, the DMA control unit 24 loads the subsequent set of transfer control information, which has been beforehand loaded into the fetch circuit 27, to the control register 26. Thereby, the DMA transfer method according to Patent Document 1 can reduce the time needed to load the subsequent set of transfer control information.